1. Field of the Invention
The present invention relates to an artificial random-number pattern (or parallel pattern) generator which is used for testing LSI circuits and, more particularly, to an artificial random-number pattern generator which is also capable of operating not only as an input or output buffer but also as a boundary scanning buffer only by means of the switching of operation mode signals.
2. Description of the Related Art
Conventionally, in order to realize in an LSI chip a built-in self testing (BIST) which has a testing function for making diagnosis of failure in or malfunction of the LSI by utilizing the artificial random-number patterns, there has been added an artificial random-number pattern generator in the LSI chip.
Such artificial random-number pattern generator is formed, for example, as shown in FIGS. 1 and 2, by a plurality of flip-flops 11-14 each having a clock signal input terminal, and an exclusive OR gate 30 for receiving outputs from at least two flip-flops out of the plurality of flip-flops. Such artificial random-number pattern generator is disclosed in "Logic Design Principles", 1986, Prentice-Hall, Pages 458 and 469, U.S.A.
The conventional random-number pattern generators as described above only have a function of generating artificial random-number patterns and can make a diagnosis of failure only in the internal circuit of the LSI. A disadvantage in such conventional generators is that it is not possible to conduct overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings of the LSI.